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DSP56362P 数据表(PDF) 67 Page - Freescale Semiconductor, Inc |
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DSP56362P 数据表(HTML) 67 Page - Freescale Semiconductor, Inc |
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67 / 152 page ![]() External Memory Expansion Port (Port A) DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-41 Figure 3-21 Synchronous Bus Timings SRAM 2 WS (TA Controlled) 3.10.4 Arbitration Timings Table 3-18 Arbitration Bus Timings1 No. Characteristics Expression 100 MHz Unit Min Max 212 CLKOUT high to BR assertion/deassertion2 1.0 4.0 ns 213 BG asserted/deasserted to CLKOUT high (setup) 4.0 — ns 214 CLKOUT high to BG deasserted/asserted (hold) 0.0 — ns 215 BB deassertion to CLKOUT high (input setup) 4.0 — ns 216 CLKOUT high to BB assertion (input hold) 0.0 — ns 217 CLKOUT high to BB assertion (output) 1.0 4.0 ns A0–A17 WR RD Data Out D0–D23 AA0–AA3 CLKOUT TA Data In D0–D23 198 199 201 200 201 211 209 207 208 210 200 203 202 205 204 206 AA0480 |
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