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DSP56362P 数据表(PDF) 87 Page - Freescale Semiconductor, Inc

部件名 DSP56362P
功能描述  24-Bit Audio Digital Signal Processor
PDF  152 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

DSP56362P 数据表(HTML) 87 Page - Freescale Semiconductor, Inc

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Serial Host Interface (SHI) I2C Protocol Timing
DSP56362 Technical Data, Rev. 4
Freescale Semiconductor
3-61
.
EXAMPLE:
For DSP clock frequency of 100 MHz (i.e. TC = 10ns), operating in a standard-mode I2C environment
(FSCL = 100 KHz (i.e. TSCL = 10µs), TR = 1000ns), with filters bypassed
Choosing HRS = 0 gives
Thus the HDM[7:0] value should be programmed to $38 (=56).
Figure 3-39 I2C Timing
Table 3-23 SCL Serial Clock Cycle generated as Master
Filters bypassed
TI
2
CCP + 2.5 × TC + 45ns + TR
Narrow filters enabled
TI
2
CCP + 2.5 × TC + 135ns + TR
Wide filters enabled
TI
2
CCP + 2.5 × TC + 223ns + TR
T
I
2CCP
10
µs 2.5 10ns 45ns 1000ns
–
–
×
–
8930ns
==
HDM 7 0
:
[]
8930ns 2
(
10ns
×
8
) 1
55.8
=
–
×
⁄
=
Start
SCL
HREQ
SDA
ACK
MSB
LSB
Stop
171
Stop
173
176
175
177
178
180
179
172
186
182
183
189
174
188
184
187
AA0275



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