DSP56362P datasheet(41/152 Pages) FREESCALE

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External Memory Expansion Port (Port A)

DSP56362 Technical Data, Rev. 4

Freescale Semiconductor

3-15

104 Address and AA valid to input data valid

tAA, tAC

100 MHz:

(WS + 0.75)

× T

C − 7.0

[WS

≥ 1]

—

10.5

7.6

105 RD assertion to input data valid

tOE

100 MHz:

(WS + 0.25)

× T

C − 7.0

[WS

≥ 1]

—5.5

—3.4

106 RD deassertion to data not valid (data hold

time)

tOHZ

0.0

—

0.0

—

107 Address valid to WR deassertion3

tAW

(WS + 0.75)

× T

C − 4.0

[WS

≥ 1]

13.5

—

10.6

—

108 Data valid to WR deassertion (data setup

time)

tDS (tDW)

100 MHz:

(WS

− 0.25) × T

C − 3.0

[WS

≥ 1]

4.5

—

3.2

—

109 Data hold time from WR deassertion

tDH

100 MHz:

0.25

× T

C − 2.0

≤ WS ≤ 3]

0.5

—

0.1

—

1.25

× T

C − 2.0

≤ WS ≤ 7]

10.5

—

8.4

—

2.25

× T

C − 2.0

[WS

≥ 8]

20.5

—

16.7

—

110 WR assertion to data active4

0.75

× T

C − 3.7

[WS = 1]

——

2.5

—

0.25

× T

C − 3.7

≤ WS ≤ 3]

——

0.0

—

−0.25 × T

C − 3.7

[WS

≥ 4]

——

0.0

—

111 WR deassertion to data high impedance4

0.25

× T

C + 0.2

≤ WS ≤ 3]

——

—

2.3

1.25

× T

C + 0.2

≤ WS ≤ 7]

——

—

10.6

2.25

× T

C + 0.2

[WS

≥ 8]

——

—

18.9

Table 3-8 SRAM Read and Write Accesses 100 and 120 MHz1 (continued)

No.

Characteristics

Symbol

Expression2

100 MHz

120 MHz

Unit

Min

Max

Min

Max

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