DSP56362P datasheet(61/152 Pages) FREESCALE

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External Memory Expansion Port (Port A)

DSP56362 Technical Data, Rev. 4

Freescale Semiconductor

3-35

186

CAS assertion to data not valid (write)

tDH

6.25

× T

C − 4.0

58.5

—

48.1

—

187

RAS assertion to data not valid (write)

tDHR

9.75

× T

C − 4.0

93.5

—

77.2

—

188

WR assertion to CAS assertion

tWCS

9.5

× T

C − 4.3

90.7

—

74.9

—

189

CAS assertion to RAS assertion (refresh)

tCSR

1.5

× T

C − 4.0

11.0

—

8.5

—

190

RAS deassertion to CAS assertion (refresh)

tRPC

4.75

× T

C − 4.0

43.5

—

35.6

—

191

RD assertion to RAS deassertion

tROH

15.5

× T

C − 4.0

151.0

—

125.2

—

192

RD assertion to data valid

tGA

× T

C − 5.7

—

134.3

—

111.0

193

RD deassertion to data not valid3

tGZ

0.0

—

0.0

—

194

WR assertion to data active

0.75

× T

C − 0.3

7.2

—

5.9

—

195

WR deassertion to data high impedance

0.25

× T

—2.5

—2.1

1 The number of wait states for out-of-page access is specified in the DCR.

2 The refresh period is specified in the DCR.

3 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t

OFF and not tGZ.

4 Either t

RCH or tRRH must be satisfied for read cycles.

Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States 100 and 120MHz1, 2 (continued)

No.

Characteristics3

Symbol

Expression

100 MHz

120 MHz

Unit

Min

Max

Min

Max

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