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DSP56362P 数据表(PDF) 44 Page - Freescale Semiconductor, Inc |
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DSP56362P 数据表(HTML) 44 Page - Freescale Semiconductor, Inc |
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44 / 152 page ![]() External Memory Expansion Port (Port A) DSP56362 Technical Data, Rev. 4 3-18 Freescale Semiconductor Figure 3-12 SRAM Write Access 3.10.2 DRAM Timing The selection guides provided in Figure 3-13 and Figure 3-16 should be used for primary selection only. Final selection should be based on the timing provided in the following tables. As an example, the selection guide suggests that 4 wait states must be used for 100 MHz operation when using Page Mode DRAM. However, by using the information in the appropriate table, a designer may choose to evaluate whether fewer wait states might be used by determining which timing prevents operation at 100 MHz, running the chip at a slightly lower frequency (e.g., 95 MHz), using faster DRAM (if it becomes available), and control factors such as capacitive and resistive load to improve overall system performance. A0–A17 WR RD Data Out D0–D23 AA0–AA3 100 102 101 107 114 110 112 111 108 109 AA0469 103 TA 119 118 |
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