DSP56362P datasheet(90/152 Pages) FREESCALE

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Enhanced Serial Audio Interface Timing

DSP56362 Technical Data, Rev. 4

3-64

Freescale Semiconductor

458 FST input (wl) to data out enable from high

impedance

—

27.0

—

459 FST input (wl) to transmitter drive enable

assertion

—

31.0

—

460 FST input (wl) setup time before TXC falling

edge

——

2.0

21.0

—

x ck

i ck

461 FST input hold time after TXC falling edge

—

4.0

0.0

—

x ck

i ck

462 Flag output valid after TXC rising edge

—

32.0

18.0

x ck

i ck

463 HCKR/HCKT clock cycle

—

40.0

—

464 HCKT input rising edge to TXC output

—

27.5

465 HCKR input rising edge to RXC output

—

27.5

1 V

CC = 3.3 V ± 0.16 V; TJ = 0°C to +100°C, CL = 50 pF

2 i ck = internal clock

x ck = external clock

i ck a = internal clock, asynchronous mode (asynchronous implies that TXC and RXC are two different clocks)

i ck s = internal clock, synchronous mode (synchronous implies that TXC and RXC are the same clock)

3 bl = bit length

wl = word length

wr = word length relative

4 TXC(SCKT pin) = transmit clock

RXC(SCKR pin) = receive clock

FST(FST pin) = transmit frame sync

FSR(FSR pin) = receive frame sync

HCKT(HCKT pin) = transmit high frequency clock

HCKR(HCKR pin) = receive high frequency clock

5 For the internal clock, the clock cycle at the pin is defined by Icyc and the ESAI control registers.

6 The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync

signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one

before last bit clock of the first word in frame.

7 Periodically sampled and not 100% tested.

Table 3-24 Enhanced Serial Audio Interface Timing (continued)

No.

Characteristics1

, 2, 3

Symbol

Expression

100 MHz

Condition4

Unit

Min

Max

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