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DSP56362P 数据表(PDF) 43 Page - Freescale Semiconductor, Inc |
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DSP56362P 数据表(HTML) 43 Page - Freescale Semiconductor, Inc |
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43 / 152 page  External Memory Expansion Port (Port A) DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-17 Figure 3-11 SRAM Read Access 118 TA setup before RD or WR deassertion5 0.25 × T C + 2.0 4.5 — 4.1 — ns 119 TA hold after RD or WR deassertion 0 — 0.0 — ns 1 All timings for 100 MHz are measured from 0.5 Vcc to .05 Vcc 2 WS is the number of wait states specified in the BCR. 3 Timings 100, 107 are guaranteed by design, not tested. 4 Timing 110, 111, and 112, are not specified for 100 MHz. 5 In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to remain active. Table 3-8 SRAM Read and Write Accesses 100 and 120 MHz1 (continued) No. Characteristics Symbol Expression2 100 MHz 120 MHz Unit Min Max Min Max A0–A17 RD WR D0–D23 AA0–AA3 115 105 106 113 104 116 117 100 AA0468 TA 119 Data In 118 |
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