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DSP56362P 数据表(PDF) 7 Page - Freescale Semiconductor, Inc |
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DSP56362P 数据表(HTML) 7 Page - Freescale Semiconductor, Inc |
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7 / 152 page ![]() DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 2-1 2 Signal/Connection Descriptions 2.1 Signal Groupings The input and output signals of the DSP56362 are organized into functional groups, which are listed in Table 2-1 and illustrated in Figure 2-1. The DSP56362 is operated from a 3.3 V supply; however, some of the inputs can tolerate 5 V. A special notice for this feature is added to the signal descriptions of those inputs. Table 2-1 DSP56362 Functional Signal Groupings Functional Group Number of Signals Detailed Description Power (VCC)20 Table 2-2 Ground (GND) 19 Table 2-3 Clock and PLL 4 Table 2-4 Address bus Port A1 1 Port A is the external memory interface port, including the external address bus, data bus, and control signals. 18 Table 2-5 Data bus 24 Table 2-6 Bus control 11 Table 2-7 Interrupt and mode control 5 Table 2-8 HDI08 Port B2 2 Port B signals are the GPIO port signals which are multiplexed with the HDI08 signals. 16 Table 2-9 SHI 5 Table 2-10 ESAI Port C3 3 Port C signals are the GPIO port signals which are multiplexed with the ESAI signals. 12 Table 2-11 Digital audio transmitter (DAX) Port D4 4 Port D signals are the GPIO port signals which are multiplexed with the DAX signals. 2 Table 2-12 Timer 1 Table 2-13 JTAG/OnCE Port 6 Table 2-14 |
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