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DSP56362P 数据表(PDF) 56 Page - Freescale Semiconductor, Inc |
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DSP56362P 数据表(HTML) 56 Page - Freescale Semiconductor, Inc |
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56 / 152 page  External Memory Expansion Port (Port A) DSP56362 Technical Data, Rev. 4 3-30 Freescale Semiconductor 191 RD assertion to RAS deassertion tROH 4.5 × T C − 4.0 221.0 — 146.0 — ns 192 RD assertion to data valid tGA 4 × T C − 7.5 — 192.5 — 125.8 ns 193 RD deassertion to data not valid3 tGZ 0.0 — 0.0 — ns 194 WR assertion to data active 0.75 × T C − 0.3 37.2 — 24.7 — ns 195 WR deassertion to data high impedance 0.25 × T C — 12.5 — 8.3 ns 1 The number of wait states for out of page access is specified in the DCR. 2 The refresh period is specified in the DCR. 3 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t OFF and not tGZ. 4 Reduced DSP clock speed allows use of DRAM out-of-page access with four Wait states. See Figure 3-16. Table 3-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2 No. Characteristics3 Symbol Expression4 80 MHz Unit Min Max 157 Random read or write cycle time tRC 9 × T C 112.5 — ns 158 RAS assertion to data valid (read) tRAC 4.75 × T C − 6.5 52.9 ns 159 CAS assertion to data valid (read) tCAC 2.25 × T C − 6.5 — 21.6 ns 160 Column address valid to data valid (read) tAA 3 × T C − 6.5 — 31.0 ns 161 CAS deassertion to data not valid (read hold time) tOFF 0.0 — ns 162 RAS deassertion to RAS assertion tRP 3.25 × T C − 4.0 36.6 — ns 163 RAS assertion pulse width tRAS 5.75 × T C − 4.0 67.9 — ns 164 CAS assertion to RAS deassertion tRSH 3.25 × T C − 4.0 36.6 — ns 165 RAS assertion to CAS deassertion tCSH 4.75 × T C − 4.0 55.4 — ns 166 CAS assertion pulse width tCAS 2.25 × T C − 4.0 24.1 — ns 167 RAS assertion to CAS assertion tRCD 2.5 × T C ± 2 29.3 33.3 ns 168 RAS assertion to column address valid tRAD 1.75 × T C ± 2 19.9 23.9 ns 169 CAS deassertion to RAS assertion tCRP 4.25 × T C − 4.0 49.1 — ns 170 CAS deassertion pulse width tCP 2.75 × T C − 4.0 30.4 — ns 171 Row address valid to RAS assertion tASR 3.25 × T C − 4.0 36.6 — ns Table 3-13 DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2 (continued) No. Characteristics3 Symbol Expression 20 MHz4 30 MHz4 Unit Min Max Min Max |
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