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DSP56362P 数据表(PDF) 85 Page - Freescale Semiconductor, Inc |
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DSP56362P 数据表(HTML) 85 Page - Freescale Semiconductor, Inc |
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85 / 152 page  Serial Host Interface (SHI) I2C Protocol Timing DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-59 3.13 Serial Host Interface (SHI) I2C Protocol Timing Table 3-22 SHI I2C Protocol Timing Standard I2C* No. Characteristics Symbol/ Expression Standard Fast-Mode Unit Min Max Min Max Tolerable spike width on SCL or SDA Filters bypassed Narrow filters enabled Wide filters enabled — — — — 0 50 100 — — — 0 50 100 ns 171 SCL clock frequency FSCL — 100 — 400 kHz 172 Bus free time TBUF 4.7 — 1.3 — µs 173 Start condition set-up time TSU;STA 4.7 — 0.6 — µs 174 Start condition hold time THD;STA 4.0 — 0.6 — µs 175 SCL low period TLOW 4.7 — 1.3 — µs 176 SCL high period THIGH 4.0 — 1.3 — µs 177 SCL and SDA rise time TR — 1000 20 + 0.1 × C b 300 ns 178 SCL and SDA fall time TF — 300 20 + 0.1 × C b 300 ns 179 Data set-up time TSU;DAT 250 — 100 — ns 180 Data hold time THD;DAT 0.0 — 0.0 0.9 µs 181 Stop condition set-up time TSU;STO 4.0 — 0.6 — µs 182 Capacitive load for each line Cb — 400 — 400 pF 183 DSP clock frequency Filters bypassed Narrow filters enabled Wide filters enabled FDSP 10.6 11.8 13.1 — — — 28.5 39.7 61.0 — — — MHz 184 HREQ in deassertion to last SCL edge (HREQ in set-up time) tSU;RQI 0.0 — 0.0 — ns 186 First SCL sampling edge to HREQ output deassertion Filters bypassed Narrow filters enabled Wide filters enabled TNG;RQO 2 × T C + 30 2 × T C + 120 2 × T C + 208 — — — 50 140 228 — — — 50 140 228 ns |
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