数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

DSP56362P 数据表(PDF) 20 Page - Freescale Semiconductor, Inc

部件名 DSP56362P
功能描述  24-Bit Audio Digital Signal Processor
PDF  152 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

DSP56362P 数据表(HTML) 20 Page - Freescale Semiconductor, Inc

Back Button DSP56362P Datasheet HTML 16Page - Freescale Semiconductor, Inc DSP56362P Datasheet HTML 17Page - Freescale Semiconductor, Inc DSP56362P Datasheet HTML 18Page - Freescale Semiconductor, Inc DSP56362P Datasheet HTML 19Page - Freescale Semiconductor, Inc DSP56362P Datasheet HTML 20Page - Freescale Semiconductor, Inc DSP56362P Datasheet HTML 21Page - Freescale Semiconductor, Inc DSP56362P Datasheet HTML 22Page - Freescale Semiconductor, Inc DSP56362P Datasheet HTML 23Page - Freescale Semiconductor, Inc DSP56362P Datasheet HTML 24Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 20 / 152 page
background image
Serial Host Interface
DSP56362 Technical Data, Rev. 4
2-14
Freescale Semiconductor
2.8
Serial Host Interface
The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode.
Table 2-10 Serial Host Interface Signals
Signal Name
Signal Type
State during
Reset
Signal Description
SCK
SCL
Input or Output
Input or Output
Tri-Stated
SPI Serial Clock—The SCK signal is an output when the SPI is
configured as a master and a Schmitt-trigger input when the SPI is
configured as a slave. When the SPI is configured as a master, the
SCK signal is derived from the internal SHI clock generator. When the
SPI is configured as a slave, the SCK signal is an input, and the clock
signal from the external master synchronizes the data transfer. The
SCK signal is ignored by the SPI if it is defined as a slave and the slave
select (SS) signal is not asserted. In both the master and slave SPI
devices, data is shifted on one edge of the SCK signal and is sampled
on the opposite edge where data is stable. Edge polarity is determined
by the SPI transfer protocol.
I2C Serial Clock—SCL carries the clock for I2C bus transactions in the
I2C mode. SCL is a Schmitt-trigger input when configured as a slave
and an open-drain output when configured as a master. SCL should
be connected to VCC through a pull-up resistor.
This signal is tri-stated during hardware, software, and individual
reset. Thus, there is no need for an external pull-up in this state.
This input is 5 V tolerant.
MISO
SDA
Input or Output
Input or Open-Drain
Output
Tri-Stated
SPI Master-In-Slave-Out—When the SPI is configured as a master,
MISO is the master data input line. The MISO signal is used in
conjunction with the MOSI signal for transmitting and receiving serial
data. This signal is a Schmitt-trigger input when configured for the SPI
Master mode, an output when configured for the SPI Slave mode, and
tri-stated if configured for the SPI Slave mode when SS is deasserted.
An external pull-up resistor is not required for SPI operation.
I2C Data and Acknowledge—In I2C mode, SDA is a Schmitt-trigger
input when receiving and an open-drain output when transmitting.
SDA should be connected to VCC through a pull-up resistor. SDA
carries the data for I2C transactions. The data in SDA must be stable
during the high period of SCL. The data in SDA is only allowed to
change when SCL is low. When the bus is free, SDA is high. The SDA
line is only allowed to change during the time SCL is high in the case
of start and stop events. A high-to-low transition of the SDA line while
SCL is high is a unique situation, and is defined as the start event. A
low-to-high transition of SDA while SCL is high is a unique situation
defined as the stop event.
This signal is tri-stated during hardware, software, and individual
reset. Thus, there is no need for an external pull-up in this state.
This input is 5 V tolerant.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com