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DSP56362P 数据表(PDF) 68 Page - Freescale Semiconductor, Inc |
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DSP56362P 数据表(HTML) 68 Page - Freescale Semiconductor, Inc |
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68 / 152 page  External Memory Expansion Port (Port A) DSP56362 Technical Data, Rev. 4 3-42 Freescale Semiconductor Figure 3-22 Bus Acquisition Timings 218 CLKOUT high to BB deassertion (output) 1.0 4.0 ns 219 BB high to BB high impedance (output) — 4.5 ns 220 CLKOUT high to address and controls active 0.25 × T C 2.5 — ns 221 CLKOUT high to address and controls high impedance 0.25 × T C —2.5 ns 222 CLKOUT high to AA active 0.25 × T C 2.5 — ns 223 CLKOUT high to AA deassertion 0.25 × T C + 4.0 3.2 6.5 ns 224 CLKOUT high to AA high impedance 0.75 × T C —7.5 ns 1 The asynchronous delays specified in the expressions are valid for DSP56362. 2 T212 is valid for Address Trace mode when the ATE bit in the OMR is set. BR is deasserted for internal accesses and asserted for external accesses. Table 3-18 Arbitration Bus Timings1 (continued) No. Characteristics Expression 100 MHz Unit Min Max A0–A17 BB AA0–AA3 CLKOUT BR BG RD, WR 212 214 216 215 220 217 213 222 AA0481 |
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