DSP56362P datasheet(73/152 Pages) FREESCALE

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Parallel Host Interface (HDI08) Timing

DSP56362 Technical Data, Rev. 4

Freescale Semiconductor

3-47

333

HCS hold time after data strobe deassertion9

—0.0

—

334

Address (AD7–AD0) setup time before HAS deassertion

(HMUX=1)

—4.7

—

335

Address (AD7–AD0) hold time after HAS deassertion (HMUX=1)

—

3.3

—

336

A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W setup time before

data strobe assertion9

•Read

• Write

—

4.7

—

337

A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W hold time after

data strobe deassertion9

—3.3

—

338

Delay from read data strobe deassertion to host request

assertion for “Last Data Register” read4, 5, 10

—

339

Delay from write data strobe deassertion to host request

assertion for “Last Data Register” write5, 8, 10

× T

—

340

Delay from data strobe assertion to host request deassertion for

“Last Data Register” read or write (HROD = 0)5, 9, 10

——

19.1

341

Delay from data strobe assertion to host request deassertion for

“Last Data Register” read or write (HROD = 1, open drain Host

Request)5, 9, 10, 11

—

300.0

342

Delay from DMA HACK deassertion to HOREQ assertion

• For “Last Data Register” read5

• For “Last Data Register” write5

• For other cases

× T

C + 19.1

1.5

× T

C + 19.1

39.1

34.1

0.0

—

343

Delay from DMA HACK assertion to HOREQ deassertion

•HROD = 05

—

—20.2

344

Delay from DMA HACK assertion to HOREQ deassertion for

“Last Data Register” read or write

• HROD = 1, open drain Host Request5, 11

—

300.0

1 See Host Port Usage Considerations in the DSP56362 User Design Manual.

2 In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.

3 V

CC = 3.3 V ± 0.16 V; TJ = 0°C to +100°C, CL = 50 pF

4 The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode.

5 The “last data register” is the register at address $7, which is the last location to be read or written in data transfers. This is

RXL/TXL in the little endian mode (HBE = 0), or RXH/TXH in the big endian mode (HBE = 1).

6 This timing is applicable only if a read from the “last data register” is followed by a read from the RXL, RXM, or RXH registers

without first polling RXDF or HREQ bits, or waiting for the assertion of the HOREQ signal.

7 This timing is applicable only if two consecutive reads from one of these registers are executed.

Table 3-20 Host Interface (HDI08) Timing1, 2 (continued)

No.

Characteristics3

Expression

100 MHz

Unit

Min

Max

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