DSP56362P datasheet(4/152 Pages) FREESCALE

4 / 152 page

Overview

DSP56362 Technical Data, Rev. 4

1-4

Freescale Semiconductor

– On-Chip Emulation (OnCE‘) module

– Joint Action Test Group (JTAG) test access port (TAP)

– Address trace mode reflects internal program RAM accesses at the external port

•

On-Chip Memories

— Modified Harvard architecture allows simultaneous access to program and data memories

— 30720 x 24-bit on-chip program ROM1 (disabled in 16-bit compatibility mode)

— 6144 x 24-bit on-chip X-data ROM1

— 6144 x 24-bit on-chip Y-data ROM1

— Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable

— 192 x 24-bit bootstrap ROM (disabled in sixteen-bit compatibility mode)

•

Off-Chip Memory Expansion

— Data memory expansion to 256K x 24-bit word memory for P, X, and Y memory using SRAM.

— Data memory expansion to 16M x 24-bit word memory for P, X, and Y memory using DRAM.

— External memory expansion port( twenty-four data pins for high speed external memory access

allowing for a large number of external accesses per sample)

— Chip select logic for glueless interface to SRAMs

— On-chip DRAM controller for glueless interface to DRAMs

•

Peripheral and Support Circuits

— Enhanced serial audio interface (ESAI) includes:

– Six serial data lines, 4 selectable as receive or transmit and 2 transmit only.

– Master or slave capability

–I2S, Sony, AC97, and other audio protocol implementations

— Serial host interface (SHI) features:

– SPI protocol with multi-master capability

–I2C protocol with single-master capability

– Ten-word receive FIFO

– Support for 8-, 16-, and 24-bit words.

— Byte-wide parallel host interface (HDI08) with DMA support

— DAX features one serial transmitter capable of supporting S/PDIF, IEC958, IEC1937, CP-340,

and AES/EBU digital audio formats; alternate configuration supports up to two GPIO lines

1. These ROMs may be factory programmed with data or programs provided by the application developer.

Instruction

Cache

Switch

Mode

Program RAM

Size

Instruction

Cache Size

X Data RAM Size Y Data RAM Size

Disabled

3072

× 24-bit

5632

× 24-bit

5632

× 24-bit

Enabled

Disabled

2048

× 24-bit

1024

× 24-bit

5632

× 24-bit

5632

× 24-bit

Disabled

Enabled

5120

× 24-bit

5632

× 24-bit

3584

× 24-bit

Enabled

4096

× 24-bit

1024

× 24-bit

5632

× 24-bit

3584

× 24-bit

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