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DSP56362P 数据表(PDF) 59 Page - Freescale Semiconductor, Inc |
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DSP56362P 数据表(HTML) 59 Page - Freescale Semiconductor, Inc |
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59 / 152 page  External Memory Expansion Port (Port A) DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-33 182 WR assertion pulse width tWP 11.5 × T C − 4.5 110.5 — ns 183 WR assertion to RAS deassertion tRWL 11.75 × T C − 4.3 113.2 — ns 184 WR assertion to CAS deassertion tCWL 10.25 × T C − 4.3 103.2 — ns 185 Data valid to CAS assertion (write) tDS 5.75 × T C − 4.0 53.5 — ns 186 CAS assertion to data not valid (write) tDH 5.25 × T C − 4.0 48.5 — ns 187 RAS assertion to data not valid (write) tDHR 7.75 × T C − 4.0 73.5 — ns 188 WR assertion to CAS assertion tWCS 6.5 × T C − 4.3 60.7 — ns 189 CAS assertion to RAS assertion (refresh) tCSR 1.5 × T C − 4.0 11.0 — ns 190 RAS deassertion to CAS assertion (refresh) tRPC 2.75 × T C − 4.0 23.5 — ns 191 RD assertion to RAS deassertion tROH 11.5 × T C − 4.0 111.0 — ns 192 RD assertion to data valid tGA 10 × T C − 7.0 93.0 ns 193 RD deassertion to data not valid3 tGZ 0.0 — ns 194 WR assertion to data active 0.75 × T C − 0.3 7.2 — ns 195 WR deassertion to data high impedance 0.25 × T C —2.5 ns 1 The number of wait states for out-of-page access is specified in the DCR. 2 The refresh period is specified in the DCR. 3 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t OFF and not tGZ. 4 The asynchronous delays specified in the expressions are valid for DSP56362. 5 Either t RCH or tRRH must be satisfied for read cycles. Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States 100 and 120MHz1, 2 No. Characteristics3 Symbol Expression 100 MHz 120 MHz Unit Min Max Min Max 157 Random read or write cycle time tRC 16 × T C 160.0 — 133.3 — ns 158 RAS assertion to data valid (read) tRAC 8.25 × T C − 5.7 — 76.8 — 63.0 ns 159 CAS assertion to data valid (read) tCAC 4.75 × T C − 5.7 — 41.8 — 33.9 ns 160 Column address valid to data valid (read) tAA 5.5 × T C − 5.7 — 49.3 40.1 ns Table 3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2 (continued) No. Characteristics3 Symbol Expression4 100 MHz Unit Min Max |
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