DSP56362P datasheet(2/152 Pages) FREESCALE

2 / 152 page

Overview

DSP56362 Technical Data, Rev. 4

1-2

Freescale Semiconductor

Figure 1-1 DSP56362 Block Diagram

Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR

Used to indicate a signal that is active when pulled low (For example, the RESET pin is active

when low.)

“asserted”

Means that a high true (active high) signal is high or that a low true (active low) signal is low

“deasserted”

Means that a high true (active high) signal is low or that a low true (active low) signal is high

Examples:

Signal/Symbol

Logic State

Signal State

Voltage*

True

Asserted

VIL / VOL

False

Deasserted

VIH / VOH

True

Asserted

VIH / VOH

False

Deasserted

VIL / VOL

Note: *Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

PLL

OnCE™

Clock

Generator

Internal

Data

Bus

Switch

YAB

XAB

PAB

YDB

XDB

PDB

GDB

MODB/IRQB

MODC/IRQC

External

Data Bus

Switch

MODD/IRQD

DSP56300

24-Bit

DDB

DAB

Peripheral

Core

Expansion Area

SHI

JTAG

RESET

MODA/IRQA

PINIT/NMI

EXTAL

Address

Control

Data

Triple

Timer

Host

Interface

ESAI

Address

Generation

Unit

Six Channel

DMA Unit

Program

Interrupt

Controller

Program

Decode

Controller

Program

Address

Generator

Data ALU

24 ¥ 24 + 56 Æ 56-bit MAC

Two 56-bit Accumulators

56-bit Barrel Shifter

Power

Mngmnt.

DRAM/SRAM

Bus

Interface

I - Cache

Control

External

Address

Bus

Switch

AA0456G

Memory

Expansion

Area

Program RAM/

Instruction

Cache

3072

× 24

Program ROM

30K

× 24

Bootstrap ROM

192

× 24

X Data

RAM

5632

× 24

ROM

6144

Y Data

RAM

5632

ROM

6144

× 24

CLKOUT

DAX

(SPDIF)

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