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DSP56362P 数据表(PDF) 46 Page - Freescale Semiconductor, Inc |
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DSP56362P 数据表(HTML) 46 Page - Freescale Semiconductor, Inc |
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46 / 152 page  External Memory Expansion Port (Port A) DSP56362 Technical Data, Rev. 4 3-20 Freescale Semiconductor 137 CAS assertion pulse width tCAS 0.75 × T C − 4.0 33.5 — 21.0 — ns 138 Last CAS deassertion to RAS deassertion5 • BRW[1:0] = 00 • BRW[1:0] = 01 • BRW[1:0] = 10 • BRW[1:0] = 11 tCRP 1.75 × T C − 6.0 3.25 × T C − 6.0 4.25 × T C − 6.0 6.25 × T C – 6.0 81.5 156.5 206.5 306.5 — — — — 52.3 102.2 135.5 202.1 — — — — ns 139 CAS deassertion pulse width tCP 0.5 × T C − 4.0 21.0 — 12.7 — ns 140 Column address valid to CAS assertion tASC 0.5 × T C − 4.0 21.0 — 12.7 — ns 141 CAS assertion to column address not valid tCAH 0.75 × T C − 4.0 33.5 — 21.0 — ns 142 Last column address valid to RAS deassertion tRAL 2 × T C − 4.0 96.0 — 62.7 — ns 143 WR deassertion to CAS assertion tRCS 0.75 × T C − 3.8 33.7 — 21.2 — ns 144 CAS deassertion to WR assertion tRCH 0.25 × T C − 3.7 8.8 — 4.6 — ns 145 CAS assertion to WR deassertion tWCH 0.5 × T C − 4.2 20.8 — 12.5 — ns 146 WR assertion pulse widt h tWP 1.5 × T C − 4.5 70.5 — 45.5 — ns 147 Last WR assertion to RAS deassertion tRWL 1.75 × T C − 4.3 83.2 — 54.0 — ns 148 WR assertion to CAS deassertion tCWL 1.75 × T C − 4.3 83.2 — 54.0 — ns 149 Data valid to CAS assertion (Write) tDS 0.25 × T C − 4.0 8.5 — 4.3 — ns 150 CAS assertion to data not valid (write) tDH 0.75 × T C − 4.0 33.5 — 21.0 — ns 151 WR assertion to CAS assertion tWCS TC − 4.3 45.7 — 29.0 — ns 152 Last RD assertion to RAS deassertion tROH 1.5 × T C − 4.0 71.0 — 46.0 — ns 153 RD assertion to data valid tGA TC − 7.5 — 42.5 — 25.8 ns 154 RD deassertion to data not valid 6 tGZ 0.0 — 0.0 — ns 155 WR assertion to data active 0.75 × T C − 0.3 37.2 — 24.7 — ns 156 WR deassertion to data high impedance 0.25 × T C — 12.5 — 8.3 ns 1 The number of wait states for Page mode access is specified in the DCR. 2 The refresh period is specified in the DCR. 3 All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t PC equals 2 × TC for read-after-read or write-after-write sequences). 4 Reduced DSP clock speed allows use of Page Mode DRAM with one Wait state. See Figure 3-13. 5 BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. 6 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t OFF and not tGZ. Table 3-9 DRAM Page Mode Timings, One Wait State (Low-Power Applications)1, 2, 3 (continued) No. Characteristics Symbol Expression 20 MHz4 30 MHz 4 Unit Min Max Min Max |
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