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DSP56362P 数据表(PDF) 57 Page - Freescale Semiconductor, Inc |
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DSP56362P 数据表(HTML) 57 Page - Freescale Semiconductor, Inc |
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57 / 152 page  External Memory Expansion Port (Port A) DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-31 172 RAS assertion to row address not valid tRAH 1.75 × T C − 4.0 17.9 — ns 173 Column address valid to CAS assertion tASC 0.75 × T C − 4.0 5.4 — ns 174 CAS assertion to column address not valid tCAH 3.25 × T C − 4.0 36.6 — ns 175 RAS assertion to column address not valid tAR 5.75 × T C − 4.0 67.9 — ns 176 Column address valid to RAS deassertion tRAL 4 × T C − 4.0 46.0 — ns 177 WR deassertion to CAS assertion tRCS 2 × T C − 3.8 21.2 — ns 178 CAS deassertion to WR5 assertion tRCH 1.25 × T C − 3.7 11.9 — ns 179 RAS deassertion to WR5 assertion tRRH 0.25 × T C − 3.0 0.1 — ns 180 CAS assertion to WR deassertion tWCH 3 × T C − 4.2 33.3 — ns 181 RAS assertion to WR deassertion tWCR 5.5 × T C − 4.2 64.6 — ns 182 WR assertion pulse width tWP 8.5 × T C − 4.5 101.8 — ns 183 WR assertion to RAS deassertion tRWL 8.75 × T C − 4.3 105.1 — ns 184 WR assertion to CAS deassertion tCWL 7.75 × T C − 4.3 92.6 — ns 185 Data valid to CAS assertion (write) tDS 4.75 × T C − 4.0 55.4 — ns 186 CAS assertion to data not valid (write) tDH 3.25 × T C − 4.0 36.6 — ns 187 RAS assertion to data not valid (write) tDHR 5.75 × T C − 4.0 67.9 — ns 188 WR assertion to CAS assertion tWCS 5.5 × T C − 4.3 64.5 — ns 189 CAS assertion to RAS assertion (refresh) tCSR 1.5 × T C − 4.0 14.8 — ns 190 RAS deassertion to CAS assertion (refresh) tRPC 1.75 × T C − 4.0 17.9 — ns 191 RD assertion to RAS deassertion tROH 8.5 × T C − 4.0 102.3 — ns 192 RD assertion to data valid tGA 7.5 × T C − 6.5 — 87.3 ns 193 RD deassertion to data not valid3 tGZ 0.0 0.0 — ns 194 WR assertion to data active 0.75 × T C − 0.3 9.1 — ns 195 WR deassertion to data high impedance 0.25 × T C —3.1 ns 1 The number of wait states for out-of-page access is specified in the DCR. 2 The refresh period is specified in the DCR. 3 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t OFF and not tGZ. 4 The asynchronous delays specified in the expressions are valid for DSP56362. 5 Either t RCH or tRRH must be satisfied for read cycles. Table 3-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2 (continued) No. Characteristics3 Symbol Expression4 80 MHz Unit Min Max |
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