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DSP56362P 数据表(PDF) 33 Page - Freescale Semiconductor, Inc |
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DSP56362P 数据表(HTML) 33 Page - Freescale Semiconductor, Inc |
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33 / 152 page  Reset, Stop, Mode Select, and Interrupt Timing DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-7 3.9 Reset, Stop, Mode Select, and Interrupt Timing Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values1 No Characteristics Expression2 100 MHz 120 MHz Unit Min Max Min Max 8 Delay from RESET assertion to all pins at reset value3 — — 26.0 26.0 ns 9 Required RESET duration4 • Power on, external clock generator, PLL disabled • Power on, external clock generator, PLL enabled • Power on, internal oscillator • During STOP, XTAL disabled (PCTL Bit 16 = 0) • During STOP, XTAL enabled (PCTL Bit 16 = 1) • During normal operation 50 × ET C 1000 × ET C 75000 × ET C 75000 × ET C 2.5 × T C 2.5 × T C 500.0 10.0 750 750 25.0 25.0 — — — — — — 416.7 8.3 625 625 20.8 20.8 — — — — — — ns µs µs µs ns ns 10 Delay from asynchronous RESET deassertion to first external address output (internal reset deassertion)5 • Minimum •Maximum 3.25 × T C + 2.0 20.25 TC + 7.50 34.5 — — 211.5 29.1 176.2 ns ns 11 Synchronous reset setup time from RESET deassertion to CLKOUT Transition 1 • Minimum •Maximum TC 5.9 — — 10.0 ns ns 12 Synchronous reset deasserted, delay time from the CLKOUT Transition 1 to the first external address output • Minimum •Maximum 3.25 × T C + 2.0 20.25 TC + 7.5 33.5 — — 207.5 ns ns 13 Mode select setup time 30.0 — 30.0 ns 14 Mode select hold time 0.0 — 0.0 ns 15 Minimum edge-triggered interrupt request assertion width 6.6 — 5.5 ns 16 Minimum edge-triggered interrupt request deassertion width 6.6 — 5.5 ns 17 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory access address out valid • Caused by first interrupt instruction fetch • Caused by first interrupt instruction execution 4.25 × T C + 2.0 7.25 × T C + 2.0 44.5 74.5 — — 37.4 62.4 ns ns 18 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-purpose transfer output valid caused by first interrupt instruction execution 10 × T C + 5.0 105.0 — 88.3 ns |
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