DSP56362P datasheet(65/152 Pages) FREESCALE

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External Memory Expansion Port (Port A)

DSP56362 Technical Data, Rev. 4

Freescale Semiconductor

3-39

209

CLKOUT high to RD deassertion

0.0

4.0

210

CLKOUT high to WR assertion5

0.5

× T

C + 4.3

[WS = 1 or

≥ 4]

6.3

9.3

All frequencies:

≤ WS ≤ 3]

1.3

4.3

211

CLKOUT high to WR deassertion

0.0

3.8

1 External bus synchronous timings should be used only for reference to the clock and not for relative timings.

2 WS is the number of wait states specified in the BCR.

3 The asynchronous delays specified in the expressions are valid for DSP56362.

4 T198 and T199 are valid for Address Trace mode if the ATE bit in the OMR is set. Use the status of BR (See T212) to

determine whether the access referenced by A0–A23 is internal or external, when this mode is enabled

5 If WS > 1, WR assertion refers to the next rising edge of CLKOUT.

Table 3-17 External Bus Synchronous Timings (SRAM Access)1 (continued)

No.

Characteristics

Expression2

, 3

100 MHz

Unit

Min

Max

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