DSP56362P datasheet(10/152 Pages) FREESCALE

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Ground

DSP56362 Technical Data, Rev. 4

2-4

Freescale Semiconductor

2.3

Ground

2.4

Clock and PLL

Table 2-3 Grounds

Ground Name

Description

GNDP

PLL Ground—GNDP is a ground dedicated for PLL use. The connection should be provided with an

extremely low-impedance path to ground. VCCP should be bypassed to GNDP by a 0.47 µF capacitor

located as close as possible to the chip package. There is one GNDP connection.

GNDP1

PLL Ground 1—GNDP1 is a ground dedicated for PLL use. The connection should be provided with an

extremely low-impedance path to ground. There is one GNDP1 connection.

GNDQ (4)

Quiet Ground—GNDQ is an isolated ground for the internal processing logic. This connection must be

tied externally to all other chip ground connections. The user must provide adequate external decoupling

capacitors. There are four GNDQ connections.

GNDA (4)

Address Bus Ground—GNDA is an isolated ground for sections of the address bus I/O drivers. This

connection must be tied externally to all other chip ground connections. The user must provide adequate

external decoupling capacitors. There are four GNDA connections.

GNDD (4)

Data Bus Ground—GNDD is an isolated ground for sections of the data bus I/O drivers. This connection

must be tied externally to all other chip ground connections. The user must provide adequate external

decoupling capacitors. There are four GNDD connections.

GNDC (2)

Bus Control Ground—GNDC is an isolated ground for the bus control I/O drivers. This connection must

be tied externally to all other chip ground connections. The user must provide adequate external

decoupling capacitors. There are two GNDC connections.

GNDH

Host Ground—GNDH is an isolated ground for the HDI08 I/O drivers. This connection must be tied

externally to all other chip ground connections. The user must provide adequate external decoupling

capacitors. There is one GNDH connection.

GNDS (2)

SHI, ESAI, DAX, and Timer Ground—GNDS is an isolated ground for the SHI, ESAI, DAX, and Timer

I/O drivers. This connection must be tied externally to all other chip ground connections. The user must

provide adequate external decoupling capacitors. There are two GNDS connections.

Table 2-4 Clock and PLL Signals

Signal Name

Type

State during Reset

Signal Description

EXTAL

Input

External Clock Input—An external clock source must be connected to EXTAL

in order to supply the clock to the internal clock generator and PLL.

This input cannot tolerate 5V.

CLKOUT

Output

Chip-Driven

Clock Output—CLKOUT provides an output clock synchronized to the internal

core clock phase.

If the PLL is enabled and both the multiplication and division factors equal one,

then CLKOUT is also synchronized to EXTAL.

If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL.

CLKOUT is not functional at frequencies of 100 MHz and above.

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