DSP56362P datasheet(31/152 Pages) FREESCALE

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EXTERNAL CLOCK OPERATION

DSP56362 Technical Data, Rev. 4

Freescale Semiconductor

3-5

3.7

EXTERNAL CLOCK OPERATION

The DSP56362 system clock is an externally supplied square wave voltage source connected to EXTAL

(Figure 3-1)

Figure 3-1 External Clock Timing

Table 3-5 Clock Operation 100 and 120 MHz Values

No.

Characteristics

Symbol

100 MHz

120 MHz

Min

Max

Min

Max

Frequency of EXTAL (EXTAL Pin Frequency)

The rise and fall time of this external clock should be 3 ns

maximum.

100.0

120.0

EXTAL input high1, 2

• With PLL disabled (46.7%–53.3% duty cycle)3

• With PLL enabled (42.5%–57.5% duty cycle)3

ETH

4.67 ns

4.25 ns

∞

157.0

µs

0.00 ns

∞

157.0

µs

EXTAL input low1, 2

• With PLL disabled (46.7%–53.3% duty cycle)3

• With PLL enabled (42.5%–57.5% duty cycle)3

ETL

4.67 ns

4.25 ns

∞

157.0

µs

4.67 ns

4.25 ns

—

1570.00

EXTAL cycle time2

• With PLL disabled

• With PLL enabled

ETC

10.00 ns

∞

273.1

µs

8.33 ns

—

273.1

µs

CLKOUT change from EXTAL fall with PLL disabled

4.3 ns

11.0 ns

EXTAL

VILC

VIHC

Midpoint

Note: The midpoint is 0.5 (VIHC + VILC).

ETH

ETL

ETC

CLKOUT With

PLL Disabled

CLKOUT With

PLL Enabled

AA0459

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