DSP56362P datasheet(34/152 Pages) FREESCALE

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Reset, Stop, Mode Select, and Interrupt Timing

DSP56362 Technical Data, Rev. 4

3-8

Freescale Semiconductor

19 Delay from address output valid caused by first interrupt

instruction execute to interrupt request deassertion for

level sensitive fast interrupts6

(3.75 + WS)

× T

C –

10.94

—Note7

—Note 7

20 Delay from RD assertion to interrupt request

deassertion for level sensitive fast interrupts6

(3.25 + WS)

× T

C –

10.94

—

Note 7

—

Note 7

21 Delay from WR assertion to interrupt request

deassertion for level sensitive fast interrupts6 8

• DRAM for all WS

• SRAM WS =1

•SRAM WS=2, 3

•SRAM WS

≥ 4

(WS + 3.5)

× T

C –

10.94

(WS + 3.5)

× T

C –

10.94

1.75

× T

C – 4.0

2.75

× T

C – 4.0

—

Note 7

—

Note 7

22 Synchronous interrupt setup time from IRQA, IRQB,

IRQC, IRQD, NMI assertion to the CLKOUT Transition 2

0.6

× T

C – 0.1

5.9

4.9

—

23 Synchronous interrupt delay time from the CLKOUT

Transition 2 to the first external address output valid

caused by the first instruction fetch after coming out of

Wait Processing state

• Minimum

•Maximum

9.25

× T

C + 1.0

24.75

× T

C + 5.0

93.5

—

252.5

78.1

—

211.2

24 Duration for IRQA assertion to recover from Stop state

0.6

× T

C − 0.1

5.9

—

4.9

—

25 Delay from IRQA assertion to fetch of first instruction

(when exiting Stop)9, 3

• PLL is not active during Stop (PCTL Bit 17 = 0) and

Stop delay is enabled (OMR Bit 6 = 0)

• PLL is not active during Stop (PCTL Bit 17 = 0) and

Stop delay is not enabled (OMR Bit 6 = 1)

• PLL is active during Stop (PCTL Bit 17 = 1) (Implies

No Stop Delay)

PLC

× ET

C × PDF +

(128 K

− PLC/2) × T

PLC

× ET

C × PDF +

(23.75

± 0.5) × T

(8.25

± 0.5) × T

1.3

232.5 ns

77.5

13.6

12.3 ms

87.5

—

64.6

—

72.9

26 Duration of level sensitive IRQA assertion to ensure

interrupt service (when exiting Stop)9, 3

• PLL is not active during Stop (PCTL Bit 17 = 0) and

Stop delay is enabled (OMR Bit 6 = 0)

• PLL is not active during Stop (PCTL Bit 17 = 0) and

Stop delay is not enabled (OMR Bit 6 = 1)

• PLL is active during Stop (PCTL Bit 17 = 1) (implies

no Stop delay)

PLC

× ET

C × PDF +

(128K

− PLC/2) × T

PLC

× ET

C × PDF +

(20.5

± 0.5) × T

5.5

× T

13.6

12.3

55.0

—

—45.8

—

Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing 100 and 120 MHz Values1 (continued)

Characteristics

Expression2

100 MHz

120 MHz

Unit

Min

Max

Min

Max

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