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DSP56362P 数据表(PDF) 42 Page - Freescale Semiconductor, Inc |
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DSP56362P 数据表(HTML) 42 Page - Freescale Semiconductor, Inc |
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42 / 152 page ![]() External Memory Expansion Port (Port A) DSP56362 Technical Data, Rev. 4 3-16 Freescale Semiconductor 112 Previous RD deassertion to data active (write)4 1.25 × T C − 4.0 [1 ≤ WS ≤ 3] —— 6.4 — ns 2.25 × T C − 4.0 [4 ≤ WS ≤ 7] —— 14.7 — 3.25 × T C − 4.0 [WS ≥ 8] —— 23.1 — 113 RD deassertion time 100 MHz: 0.75 × T C − 4.0 [1 ≤ WS ≤ 3] 3.5 — 2.2 — ns 1.75 × T C − 4.0 [4 ≤ WS ≤ 7] 13.5 — 10.6 — 2.75 × T C − 4.0 [WS ≥ 8] 23.5 — 18.9 — 114 WR deassertion time 100 MHz: 0.5 × T C − 4.0 [WS = 1] 1.0 — 0.2 — ns TC − 2.0 [2 ≤ WS ≤ 3] 6.0 — 6.3 — 2.5 × T C − 4.0 [4 ≤ WS ≤ 7] 21.0 — 16.8 — 3.5 × T C − 4.0 [WS ≥ 8] 31.0 — 25.2 — 115 Address valid to RD assertion 100 MHz: 0.5 × T C − 4.0 1.0 — 0.2 — ns 116 RD assertion pulse width 100 MHz: (WS + 0.25) × T C −4.0 8.5 — 6.4 — ns 117 RD deassertion to address not valid 100 MHz: 0.25 × T C − 2.0 [1 ≤ WS ≤ 3] 0.5 — 0.1 — ns 1.25 × T C − 2.0 [4 ≤ WS ≤ 7] 10.5 — 8.4 — 2.25 × T C − 2.0 [WS ≥ 8] 20.5 — 16.7 — Table 3-8 SRAM Read and Write Accesses 100 and 120 MHz1 (continued) No. Characteristics Symbol Expression2 100 MHz 120 MHz Unit Min Max Min Max |
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