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H8SX1663 数据表(PDF) 351 Page - Renesas Technology Corp

部件名 H8SX1663
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX1663 数据表(HTML) 351 Page - Renesas Technology Corp

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Section 6 Bus Controller (BSC)
Rev.1.00 Jun. 07, 2006 Page 299 of 1102
REJ09B0294-0100
(7) Idle Cycle for Accessing to DRAM/SDRAM Space
In the following read cycles, when the DRAM/SDRAM space is accessed in a full access, the Tp
and Tr cycles are also counted as idle cycles.
Figures 6.96 and 6.97 show timing examples of full accesses to the DRAM/SDRAM space when
four idle cycles are inserted.
When accessing the DRAM/SDRAM space, the Ti cycles are inserted so that the sum of the
numbers of Tp (precharge), Tr (row address output), and Ti cycles satisfies the specified number
of idle cycles. The Ti cycles are inserted before the column address output cycle.
While the SDRAM space is accessed in a full access, the
CS2 signal is driven low even in an idle
cycle.
The idle cycle insertion is enabled even in a fast-page access in RAS down mode. The specified
number of idle cycles is inserted. Figure 6.98 shows a timing example of the idle cycle insertion in
RAS down mode.
B
φ
Address bus
RD
RAS
LLCAS
T
1
T
2
T
3
T
r
T
p
T
i
T
c1
T
i
T
c2
External space read
DRAM space read
Data bus
Figure 6.96 Example of DRAM Full Access after External Read (CAST = 0)



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