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H8SX1663 数据表(PDF) 348 Page - Renesas Technology Corp |
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H8SX1663 数据表(HTML) 348 Page - Renesas Technology Corp |
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348 / 1158 page  Section 6 Bus Controller (BSC) Rev.1.00 Jun. 07, 2006 Page 296 of 1102 REJ09B0294-0100 (4) External Access after Single Address Transfer Write If an external access occurs after a single address transfer write while bit IDLS3 in IDLCR is set to 1, idle cycles specified by bits IDLCA1 and IDLCA0 are inserted at the start of the external access (n = 0 to 7). Figure 6.93 shows an example of the operation in this case. In this example, bus cycle A is a single address transfer (write cycle) and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a conflict occurs in bus cycle B between the external device write data and this LSI write data. In (b), an idle cycle is inserted, and a data conflict is prevented. Output floating time is long. Data conflict Bus cycle A Bus cycle B (a) No idle cycle inserted (IDLS3 = 0) B φ Address bus CS (area A) CS (area B) LLWR DACK Data bus T 1 T 2 T 3 T 1 T 2 (b) Idle cycle inserted Bus cycle A Bus cycle B T 1 T 2 T 3 T 1 T i T 2 (IDLS3 = 1, IDLCA1 = 0, IDLCA0 = 0) Figure 6.93 Example of Idle Cycle Operation (Write after Single Address Transfer Write) |
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