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H8SX1663 数据表(PDF) 346 Page - Renesas Technology Corp

部件名 H8SX1663
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX1663 数据表(HTML) 346 Page - Renesas Technology Corp

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Section 6 Bus Controller (BSC)
Rev.1.00 Jun. 07, 2006 Page 294 of 1102
REJ09B0294-0100
(2) Write after Read
If an external write occurs after an external read while bit IDLS0 in IDLCR is set to 1, idle cycles
specified by bits IDLCA1 and IDLCA0 when bit IDLSELn in IDLCR is cleared to 0 when
IDLSELn = 0, or bits IDLCB1 and IDLCB0 when IDLSELn is set to 1 are inserted at the start of
the write cycle (n = 0 to 7).
Figure 6.91 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a conflict occurs in bus cycle B between the read data from ROM
and the CPU write data. In (b), an idle cycle is inserted, and a data conflict is prevented.
Data hold
time is long.
Data conflict
Bus cycle A
Bus cycle B
B
φ
Address bus
CS (area A)
CS (area B)
RD
LLWR
Data bus
T
1
T
2
T
3
T
1
T
2
(b) Idle cycle inserted
Bus cycle A
Bus cycle B
T
1
T
2
T
3
T
1
T
i
T
2
(a) No idle cycle inserted
(IDLS0 = 0)
(IDLS0 = 1, IDLSELn = 0, IDLCA1 = 0, IDLCA0 = 0)
Figure 6.91 Example of Idle Cycle Operation (Write after Read)



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