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H8SX1663 数据表(PDF) 344 Page - Renesas Technology Corp |
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H8SX1663 数据表(HTML) 344 Page - Renesas Technology Corp |
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344 / 1158 page ![]() Section 6 Bus Controller (BSC) Rev.1.00 Jun. 07, 2006 Page 292 of 1102 REJ09B0294-0100 Table 6.28 Number of Idle Cycle Insertion Selection in Each Area Bit Settings IDLSn IDLSELn Area of Previous Access Insertion Condition n Setting n = 0 to 7 0 1 2 3 4 5 6 7 0 Invalid 0 A A A A A A A A Consecutive reads in different areas 1 1 1 B B B B B B B B 0 Invalid 0 A A A A A A A A Write after read 0 1 1 B B B B B B B B 0 Invalid Read after write 2 1 A 0 Invalid External access after single address transfer 3 1 A [Legend] A: Number of idle cycle insertion A is selected. B: Number of idle cycle insertion B is selected. Invalid: No idle cycle is inserted for the corresponding condition. Table 6.29 Number of Idle Cycles Inserted Bit Settings A B IDLCA1 IDLCA0 IDLCB1 IDLCB0 Number of Cycles 0 0 0 0 0 1 0 1 0 1 2 1 0 1 0 3 1 1 1 1 4 |
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