H8SX1663 datasheet(129/1158 Pages) RENESAS

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Section 4 Exception Handling

Rev.1.00 Jun. 07, 2006 Page 77 of 1102

REJ09B0294-0100

Section 4 Exception Handling

4.1

Exception Handling Types and Priority

As table 4.1 indicates, exception handling is caused by a reset, a trace, an address error, an

interrupt, a trap instruction, a sleep instruction, and an illegal instruction (general illegal

instruction or slot illegal instruction). Exception handling is prioritized as shown in table 4.1. If

two or more exceptions occur simultaneously, they are accepted and processed in order of priority.

Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt

control mode. For details on the interrupt control mode, see section 5, Interrupt Controller.

Table 4.1

Exception Types and Priority

Priority

Exception Type

Exception Handling Start Timing

High

Reset

Exception handling starts at the timing of level change from

low to high on the

RES pin, or when the watchdog timer

overflows. The CPU enters the reset state when the

RES

pin is low.

Illegal instruction

Exception handling starts when an undefined code is

executed.

Trace*

Exception handling starts after execution of the current

instruction or exception handling, if the trace (T) bit in EXR

is set to 1.

Address error

After an address error has occurred, exception handling

starts on completion of instruction execution.

Interrupt

Exception handling starts after execution of the current

instruction or exception handling, if an interrupt request has

occurred.*

Sleep instruction

Exception handling starts by execution of a sleep instruction

(SLEEP), if the SSBY bit in SBYCR is set to 0 and the

SLPIE bit in SBYCR is set to 1.

Low

Trap instruction*

Exception handling starts by execution of a trap instruction

(TRAPA).

Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not

executed after execution of an RTE instruction.

2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC

instruction execution, or on completion of reset exception handling.

3. Trap instruction exception handling requests and sleep instruction exception handling

requests are accepted at all times in program execution state.

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