H8SX1663 datasheet(137/1158 Pages) RENESAS

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Section 4 Exception Handling

Rev.1.00 Jun. 07, 2006 Page 85 of 1102

REJ09B0294-0100

4.5.2

Address Error Exception Handling

When an address error occurs, address error exception handling starts after the bus cycle causing

the address error ends and current instruction execution completes. The address error exception

handling is as follows:

1. The contents of PC, CCR, and EXR are saved in the stack.

2. The interrupt mask bit is updated and the T bit is cleared to 0.

3. An exception handling vector table address corresponding to the address error is generated, the

start address of the exception service routine is loaded from the vector table to PC, and

program execution starts from that address.

Even though an address error occurs during a transition to an address error exception handling, the

address error is not accepted. This prevents an address error from occurring due to stacking for

exception handling, thereby preventing infinitive stacking.

If the SP contents are not a multiple of 2 when an address error exception handling occurs, the

stacked values (PC, CCR, and EXR) are undefined.

When an address error occurs, the following is performed to halt the DTC and DMAC.

• The ERR bit of DTCCR in the DTC is set to 1.

• The ERRF bit of DMDR_0 in the DMAC is set to 1.

• The DTE bits of DMDRs for all channels in the DMAC are cleared to 0 to forcibly terminate

transfer.

Table 4.6 shows the state of CCR and EXR after execution of the address error exception

handling.

Table 4.6

Status of CCR and EXR after Address Error Exception Handling

CCR

EXR

Interrupt Control Mode

I2 to I0



[Legend]

Set to 1

Cleared to 0

:

Retains the previous value.

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