H8SX1663 datasheet(136/1158 Pages) RENESAS

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Section 4 Exception Handling

Rev.1.00 Jun. 07, 2006 Page 84 of 1102

REJ09B0294-0100

4.5

Address Error

4.5.1

Address Error Source

Instruction fetch, stack operation, or data read/write shown in table 4.5 may cause an address

error.

Table 4.5

Bus Cycle and Address Error

Bus Cycle

Type

Bus Master

Description

Address Error

Instruction fetch

CPU

Fetches instructions from even addresses

No (normal)

Fetches instructions from odd addresses

Occurs

Fetches instructions from areas other than on-chip

peripheral module space*

No (normal)

Fetches instructions from on-chip peripheral module

space*

Occurs

Fetches instructions from external memory space in

single-chip mode

Occurs

Fetches instructions from access prohibited area.*

Occurs

Stack operation

CPU

Accesses stack when the stack pointer value is even

address

No (normal)

Accesses stack when the stack pointer value is odd

Occurs

Data read/write

CPU

Accesses word data from even addresses

No (normal)

Accesses word data from odd addresses

No (normal)

Accesses external memory space in single-chip mode

Occurs

Accesses to access prohibited area*

Occurs

Data read/write

DTC or DMAC

Accesses word data from even addresses

No (normal)

Accesses word data from odd addresses

No (normal)

Accesses external memory space in single-chip mode

Occurs

Accesses to access prohibited area*

Occurs

Single address

transfer

DMAC

Address access space is the external memory space for

single address transfer

No (normal)

Address access space is not the external memory space

for single address transfer

Occurs

Notes: 1. For on-chip peripheral module space, see section 6, Bus Controller (BSC).

2. For the access prohibited area, refer to figure 3.1 in section 3.4, Address Map.

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