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H8SX1663 数据表(PDF) 146 Page - Renesas Technology Corp |
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H8SX1663 数据表(HTML) 146 Page - Renesas Technology Corp |
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146 / 1158 page  Section 5 Interrupt Controller Rev.1.00 Jun. 07, 2006 Page 94 of 1102 REJ09B0294-0100 A block diagram of the interrupt controller is shown in figure 5.1. INTCR IPR NMI input IRQ11 to HRQ0 input Internal interrupt sources WOVI to RESUME INTM1, INTM0 NMIEG NMI input unit IRQ input unit CPU priority DTC priority Interrupt controller Priority determination Source selector CPU interrupt request CPU vector DTC vector Activation request clear signal DTC activation request I I2 to I0 CCR EXR CPU DTC INTCR: CPUPCR: ISCR: IER: ISR: Interrupt control register CPU priority control register IRQ sense control register IRQ enable register IRQ status register SSIER: IPR: DTCER: DTCCR: Software standby release IRQ enable register Interrupt priority register DTC enable register DTC control register [Legend] ISCR SSIER IER DTCER DTC priority control DTCCR ISR DMAC activation permission DMDR DMAC DMAC priority control CPUPCR IRQ15 input TM32K Figure 5.1 Block Diagram of Interrupt Controller |
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