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H8SX1663 数据表(PDF) 150 Page - Renesas Technology Corp

部件名 H8SX1663
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX1663 数据表(HTML) 150 Page - Renesas Technology Corp

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Section 5 Interrupt Controller
Rev.1.00 Jun. 07, 2006 Page 98 of 1102
REJ09B0294-0100
Bit
Bit Name
Initial
Value
R/W
Description
2
1
0
CPUP2
CPUP1
CPUP0
0
0
0
R/(W)*
R/(W)*
R/(W)*
CPU Priority Level 2 to 0
These bits set the CPU priority level. When the
CPUPCE is set to 1, the CPU priority control function
over the DTC and DMAC becomes valid and the priority
of CPU processing is assigned in accordance with the
settings of bits CPUP2 to CPUP0.
000: Priority level 0 (lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (highest)
Note:
*
When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits
cannot be modified.
5.3.3
Interrupt Priority Registers A to I, K, L, Q, and R
(IPRA to IPRI, IPRK, IPRL, IPRQ, and IPRR)
IPR sets priory (levels 7 to 0) for interrupts other than NMI.
Setting a value in the range from B'000 to B'111 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4,
and 2 to 0 assigns a priority level to the corresponding interrupt. For the correspondence between
the interrupt sources and the IPR settings, see table 5.2.
Bit
Bit Name
Initial Value
R/W
15
0
R
14
IPR14
1
R/W
13
IPR13
1
R/W
12
IPR12
1
R/W
11
0
R
10
IPR10
1
R/W
9
IPR9
1
R/W
8
IPR8
1
R/W
Bit
Bit Name
Initial Value
R/W
7
0
R
6
IPR6
1
R/W
5
IPR5
1
R/W
4
IPR4
1
R/W
3
0
R
2
IPR2
1
R/W
1
IPR1
1
R/W
0
IPR0
1
R/W



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