H8SX1663 datasheet(149/1158 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.1.00 Jun. 07, 2006 Page 97 of 1102

REJ09B0294-0100

5.3.2

CPU Priority Control Register (CPUPCR)

CPUPCR sets whether or not the CPU has priority over the DTC and DMAC. The interrupt

exception handling by the CPU can be given priority over that of the DTC and DMAC transfer.

The priority level of the DTC is set by bits DTCP2 to DTCP0 in CPUPCR. The priority level of

the DMAC is set by the DMAC control register for each channel.

Bit

Bit Name

Initial Value

R/W

Note: * When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits cannot be modified.

CPUPCE

R/W

DTCP2

R/W

DTCP1

R/W

DTCP0

R/W

IPSETE

R/W

CPUP2

R/(W)*

CPUP1

R/(W)*

CPUP0

R/(W)*

Bit

Bit Name

Initial

Value

R/W

Description

CPUPCE

R/W

CPU Priority Control Enable

Controls the CPU priority control function. Setting this bit

to 1 enables the CPU priority control over the DTC and

DMAC.

0: CPU always has the lowest priority

1: CPU priority control enabled

DTCP2

DTCP1

DTCP0

R/W

DTC Priority Level 2 to 0

These bits set the DTC priority level.

000: Priority level 0 (lowest)

001: Priority level 1

010: Priority level 2

011: Priority level 3

100: Priority level 4

101: Priority level 5

110: Priority level 6

111: Priority level 7 (highest)

IPSETE

R/W

Interrupt Priority Set Enable

Controls the function which automatically assigns the

interrupt priority level of the CPU. Setting this bit to 1

automatically sets bits CPUP2 to CPUP0 by the CPU

interrupt mask bit (I bit in CCR or bits I2 to I0 in EXR).

0: Bits CPUP2 to CPUP0 are not updated automatically

1: The interrupt mask bit value is reflected in bits CPUP2

to CPUP0

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