H8SX1663 datasheet(158/1158 Pages) RENESAS

部件名	H8SX1663

功能描述	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1158 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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158 / 1158 page

Section 5 Interrupt Controller

Rev.1.00 Jun. 07, 2006 Page 106 of 1102

REJ09B0294-0100

5.3.6

IRQ Status Register (ISR)

ISR is an IRQ15, and IRQ11 to IRQ0 interrupt request register.

Bit

Bit Name

Initial Value

R/W

IRQ15F

R/(W)*



R/W



R/W



R/W

IRQ11F

R/(W)*

IRQ10F

R/(W)*

IRQ9F

R/(W)*

IRQ8F

R/(W)*

Bit

Bit Name

Initial Value

R/W

Note:

Only 0 can be written, to clear the flag. The bit manipulation instructions or memory operation instructions should

be used to clear the flag.

IRQ7F

R/(W)*

IRQ6F

R/(W)*

IRQ5F

R/(W)*

IRQ4F

R/(W)*

IRQ3F

R/(W)*

IRQ2F

R/(W)*

IRQ1F

R/(W)*

IRQ0F

R/(W)*

Bit

Bit Name

Initial

Value

R/W

Description

IRQ15F

R/(W)*

[Setting condition]

• When the interrupt selected by ISCR occurs

[Clearing conditions]

• Writing 0 after reading IRQnF = 1 (n = 15)

• When IRQn interrupt exception handling is executed

while falling-edge sensing is selected

14 to 12



All 0

R/W

Reserved

These bits are always read as 0. The write value should

always be 0.

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