H8SX1663 datasheet(161/1158 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.1.00 Jun. 07, 2006 Page 109 of 1102

REJ09B0294-0100

5.4

Interrupt Sources

5.4.1

External Interrupts

There are thirteen external interrupts: NMI and IRQ11 to IRQ0. These interrupts can be used to

leave software standby mode.

(1)

NMI Interrupts

Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always accepted by

the CPU regardless of the interrupt control mode or the settings of the CPU interrupt mask bits.

The NMIEG bit in INTCR selects whether an interrupt is requested at the rising or falling edge on

the NMI pin.

When an NMI interrupt is generated, the interrupt controller determines that an error has occurred,

and performs the following procedure.

• Sets the ERR bit of DTCCR in the DTC to 1.

• Sets the ERRF bit of DMDR_0 in the DMAC to 1

• Clears the DTE bits of DMDRs for all channels in the DMAC to 0 to forcibly terminate

transfer

(2)

IRQn Interrupts

An IRQn interrupt is requested by a signal input on pins

IRQ11 to IRQ0. IRQn (n = 11 to 0) have

the following features:

• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling

edge, rising edge, or both edges, on pins

IRQn.

• Enabling or disabling of interrupt requests IRQn can be selected by IER.

• The interrupt priority can be set by IPR.

• The status of interrupt requests IRQn is indicated in ISR. ISR flags can be cleared to 0 by

software. The bit manipulation instructions and memory operation instructions should be used

to clear the flag.

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