H8SX1663 datasheet(163/1158 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.1.00 Jun. 07, 2006 Page 111 of 1102

REJ09B0294-0100

5.5

Interrupt Exception Handling Vector Table

Table 5.2 lists interrupt exception handling sources, vector address offsets, and interrupt priority.

In the default priority order, a lower vector number corresponds to a higher priority. When

interrupt control mode 2 is set, priority levels can be changed by setting the IPR contents. The

priority for interrupt sources allocated to the same level in IPR follows the default priority, that is,

they are fixed.

Table 5.2

Interrupt Sources, Vector Address Offsets, and Interrupt Priority

Classification

Interrupt Source

Vector

Number

Vector

Address

Offset*

IPR

Priority

DTC

Activation

DMAC

Activation

External pin

NMI

H'001C



High



External pin

IRQ0

H'0100

IPRA14 to IPRA12



IRQ1

H'0104

IPRA10 to IPRA8



IRQ2

H'0108

IPRA6 to IPRA4



IRQ3

H'010C

IPRA2 to IPRA0



IRQ4

H'0110

IPRB14 to IPRB12



IRQ5

H'0114

IPRB10 to IPRB8



IRQ6

H'0118

IPRB6 to IPRB4



IRQ7

H'011C

IPRB2 to IPRB0



IRQ8

H'0120

IPRC14 to IPRC12



IRQ9

H'0124

IPRC10 to IPRC8



IRQ10

H'0128

IPRC6 to IPRC4



IRQ11

H'012C

IPRC2 to IPRC0



H'0130



Reserved for

system use

H'0134



H'0138



TM32K

32KOVI (IRQ15) 79

H'013C

IPRD2 to IPRD0



Reserved for

system use

H'0140



WDT

WOVI

H'0144

IPRE10 to IPRE8

Low



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