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H8SX1663 数据表(PDF) 220 Page - Renesas Technology Corp |
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H8SX1663 数据表(HTML) 220 Page - Renesas Technology Corp |
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220 / 1158 page ![]() Section 6 Bus Controller (BSC) Rev.1.00 Jun. 07, 2006 Page 168 of 1102 REJ09B0294-0100 6.3 Bus Configuration Figure 6.5 shows the internal bus configuration of this LSI. The internal bus of this LSI consists of the following three types. • Internal system bus A bus that connects the CPU, DTC, DMAC, on-chip RAM, on-chip ROM, internal peripheral bus, and external access bus. • Internal peripheral bus A bus that accesses registers in the bus controller, interrupt controller, and DMAC, and registers of peripheral modules such as SCI and timer. • External access cycle A bus that accesses external devices via the external bus interface. CPU DTC B φ synchronization P φ synchronization I φ synchronization Bus controller, interrupt controller, power-down controller External bus interface Peripheral functions On-chip RAM Internal system bus On-chip ROM Internal peripheral bus Write data buffer Write data buffer External access bus DMAC Figure 6.5 Internal Bus Configuration |
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