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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8SX1663 数据表(PDF) 217 Page - Renesas Technology Corp |
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H8SX1663 数据表(HTML) 217 Page - Renesas Technology Corp |
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217 / 1158 page  Section 6 Bus Controller (BSC) Rev.1.00 Jun. 07, 2006 Page 165 of 1102 REJ09B0294-0100 Bit Bit Name Initial Value R/W Description 10 9 8 RTCK2 RTCK1 RTCK0 0 0 0 R/W R/W R/W Refresh Counter Clock Select Select the clock used to count up the refresh counter from the seven internal clocks generated by dividing the on-chip peripheral module clock (P φ). When the clock is selected, the refresh counter starts to count up. 000: Counting halted 001: Counts on P φ/2 001: Counts on P φ/8 001: Counts on P φ/32 001: Counts on P φ/128 001: Counts on P φ/512 001: Counts on P φ/2048 001: Counts on P φ/4096 7 RFSHE 0 R/W Refresh Control Enables or disables refresh control. When refresh control is disabled, the refresh timer can be used as the interval timer. In single-chip activation mode, the setting of this bit should be made after setting the EXPE bit in SYSCR to 1. For SYSCR, see section 3, MCU Operating Modes. 0: Refresh control enabled 1: Refresh control disabled 6 5 4 RLW2 RLW1 RLW0 0 0 0 R/W R/W R/W Refresh Cycle Wait Control Select the number of wait cycles during a CAS before RAS refresh cycle for the DRAM interface and an auto- refresh cycle for the SDRAM interface. 000: No wait cycle inserted 001: One wait cycle inserted 010: Two wait cycles inserted 010: Three wait cycles inserted 010: Four wait cycles inserted 010: Five wait cycles inserted 010: Six wait cycles inserted 010: Seven wait cycles inserted |
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