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H8SX1663 数据表(PDF) 215 Page - Renesas Technology Corp |
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H8SX1663 数据表(HTML) 215 Page - Renesas Technology Corp |
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215 / 1158 page ![]() Section 6 Bus Controller (BSC) Rev.1.00 Jun. 07, 2006 Page 163 of 1102 REJ09B0294-0100 Bit Bit Name Initial Value R/W Description 6 to 1 All 0 R Reserved The initial value should not be changed. 0 TRWL 0 R/W Write-Precharge Delay Control Specifies the time until the precharge command is issued after the write command is issued to the SDRAM. Setting this bit to 1 inserts one wait cycle after the write command is issued. 0: No wait cycle inserted 1: One wait cycle inserted 6.2.16 Refresh Control Register (REFCR) REFCR specifies the refresh type for the DRAM/SDRAM interface. Bit Bit Name Initial Value R/W 15 CMF 0 R/(W)* 14 CMIE 0 R/W 13 RCW1 0 R/W 12 RCW0 0 R/W 11 0 R 10 RTCK2 0 R/W 9 RTCK1 0 R/W 8 RTCK0 0 R/W Bit Bit Name Initial Value R/W Note: * Only 0 can be written to this bit, to clear the flag. 7 RFSHE 0 R/W 6 RLW2 0 R/W 5 RLW1 0 R/W 4 RLW0 0 R/W 3 SLFRF 0 R/W 2 TPCS2 0 R/W 1 TPCS1 0 R/W 0 TPCS0 0 R/W |
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