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H8SX1663 数据表(PDF) 212 Page - Renesas Technology Corp

部件名 H8SX1663
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX1663 数据表(HTML) 212 Page - Renesas Technology Corp

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Section 6 Bus Controller (BSC)
Rev.1.00 Jun. 07, 2006 Page 160 of 1102
REJ09B0294-0100
B
φ
Address
RAS
(When RAST = 0)
RAS
(When RAST = 1)
LUCAS, LLCAS
Tp
Tr
Tc1
Tc2
Row address
Column address
Bus cycle
Figure 6.4
RAS Assertion Timing (Column Address Output for 2 cycles
in Full Access Mode)
6.2.14
DRAM Access Control Register (DRACCR)
DRACCR specifies the settings for the DRAM/SDRAM interface. Rewrite this register while the
DRAM/SDRAM is not accessed.
Bit
Bit Name
Initial Value
R/W
15
0
R
14
0
R
13
TPC1
0
R/W
12
TPC0
0
R/W
11
0
R
10
0
R
9
RCD1
0
R/W
8
RCD0
0
R/W
Bit
Bit Name
Initial Value
R/W
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
0
R



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