H8SX1663 datasheet(210/1158 Pages) RENESAS

210 / 1158 page

Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 158 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

RCDM

R/W

RAS Down Mode

Selects the

RAS signal state while a DRAM access is

halted when a basic bus interface area or an on-chip

I/O register is accessed: keep the

RAS signal low (RAS

down mode) and high (

RAS up mode).

This bit is effective when BE = 1. Clearing this bit to 0

with RCDM = 1 in

RAS down mode cancels the RAS

down mode and the

RAS signal goes high.

If the

RAS down mode is selected for the SDRAM

interface, the READ/WRIT command is issued without

issuance of the ACTV command when the same row

address is accessed consecutively.

0: RAS up mode when the DRAM/SDRAM is accessed

1: RAS down mode when the DRAM/SDRAM is

accessed

DDS

R/W

DMAC Single Address Transfer Option

Selects whether a DMAC single address transfer

through the DRAM/SDRAM interface is enabled only in

full access mode or is also enabled in fast-page access

mode.

When clearing the BE bit to 0 to disable a burst access

to the DRAM/SDRAM interface, a DMAC single address

transfer is performed in full access mode regardless of

this bit.

This bit does not affect an external access by other bus

masters or a DMAC dual address transfer. Setting this

bit to 1 changes the

DACK output timing.

0: DMAC single address transfer through the

DRAM/SDRAM is enabled only in full access mode

1: DMAC single address transfer through the

DRAM/SDRAM is also enabled in fast-page access

mode

H8SX1663 数据表(PDF) 210 Page - Renesas Technology Corp

H8SX1663 数据表(HTML) 210 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载