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H8SX1663 数据表(PDF) 207 Page - Renesas Technology Corp

部件名 H8SX1663
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX1663 数据表(HTML) 207 Page - Renesas Technology Corp

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Section 6 Bus Controller (BSC)
Rev.1.00 Jun. 07, 2006 Page 155 of 1102
REJ09B0294-0100
6.2.12
Address/Data Multiplexed I/O Control Register (MPXCR)
MPXCR specifies the address/data multiplexed I/O interface.
Bit
Bit Name
Initial Value
R/W
15
MPXE7
0
R/W
14
MPXE6
0
R/W
13
MPXE5
0
R/W
12
MPXE4
0
R/W
11
MPXE3
0
R/W
10
0
R
9
0
R
8
0
R
Bit
Bit Name
Initial Value
R/W
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
ADDEX
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
15
14
13
12
11
MPXE7
MPXE6
MPXE5
MPXE4
MPXE3
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Address/Data Multiplexed I/O Interface Select
Specifies the bus interface for the corresponding area.
To set this bit to 1, clear the BCSELn bit in SRAMCR to
0.
0: Area n is specified as a basic interface or a byte
control SRAM interface.
1: Area n is specified as an address/data multiplexed
I/O interface
(n = 7 to 3)
10 to 1
All 0
R
Reserved
These are read-only bits and cannot be modified.
0
ADDEX
0
R/W
Address Output Cycle Extension
Specifies whether a wait cycle is inserted for the
address output cycle of address/data multiplexed I/O
interface.
0: No wait cycle is inserted for the address output cycle
1: One wait cycle is inserted for the address output
cycle



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