H8SX1663 datasheet(209/1158 Pages) RENESAS

209 / 1158 page

Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 157 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

RAST

R/W

RAS Assertion Timing Select

Selects whether the

RAS signal is asserted at the rising

edge or falling edge of the B

φ signal in the Tr cycle

during a DRAM access. The relationship between this

bit and

RAS assertion timing is shown in figure 6.4.

When SDRAM is used, the setting of this bit does not

affect operation.

0: RAS signal is asserted at the falling edge of the Bf

signal in the Tr cycle

1: RAS signal is asserted at the rising edge of the Bf

signal in the Tr cycle



Reserved

The initial value should not be changed.

CAST

R/W

Column Address Output Cycle Count Select

Selects whether the number of column address output

cycles is two or three during a DRAM access.

When SDRAM is used, the setting of this bit does not

affect operation.

0: Column address is output for two cycles

1: Column address is output for three cycles

R/W

Burst Access Enable

Enables or disables a burst access to the

DRAM/SDRAM. The DRAM/SDRAM is accessed in

high-speed page mode. When DRAM with the EDO

page mode is used, connect the

OE signal of this LSI to

the

OE signal of DRAM.

0: DRAM/SDRAM is accessed with full access

1: DRAM/SDRAM is accessed in high-speed page

mode

H8SX1663 数据表(PDF) 209 Page - Renesas Technology Corp

H8SX1663 数据表(HTML) 209 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载