H8SX1663 datasheet(208/1158 Pages) RENESAS

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Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 156 of 1102

REJ09B0294-0100

6.2.13

DRAM Control Register (DRAMCR)

DRAMCR specifies the DRAM/SDRAM interface. Rewrite this register while the

DRAM/SDRAM is not accessed.

Bit

Bit Name

Initial Value

R/W

DRAME

R/W

DTYPE

R/W



OEE

R/W

RAST

R/W



CAST

R/W

Bit

Bit Name

Initial Value

R/W

RCDM

R/W

DDS

R/W



R/W



R/W

MXC1

R/W

MXC0

R/W

Bit

Bit Name

Initial

Value

R/W

Description

DRAME

R/W

Area 2 DRAM Interface Select

Selects whether or not area 2 is specified as the

DRAM/SDRAM interface. When this bit is set to 1,

select the type of DRAM to be used in area 2 with the

DTYPE bit. When this bit is set to 1, the BCSEL2 bit in

SRAMCR should be set to 0.

0: Basic bus interface or byte-control SRAM interface

1: DRAM/SDRAM interface

DTYPE

R/W

DRAM Select

Selects the type of DRAM to be used in area 2.

0: DRAM is used in area 2

1: SDRAM is used in area 2

13, 12



All 0

Reserved

The initial value should not be changed.

OEE

R/W

OE Output Enable

The

OE signal is output when DRAM with the EDO

page mode is connected, whereas the CKE signal is

output when SDRAM is connected.

OE/CKE signal output disabled (the OE/CKE pin can

be used as an I/O port)

OE/CKE signal enabled

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