H8SX1663 datasheet(222/1158 Pages) RENESAS

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Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 170 of 1102

REJ09B0294-0100

For example, in an external address space access where the frequency rate of I

φ and Bφ is n : 1,

the operation is performed in synchronization with B

φ. In this case, external 2-state access space is

2n cycles and external 3-state access space is 3n cycles (no wait cycles is inserted) if the number

of access cycles is counted based on I

φ.

If the frequencies of I

φ, Pφ and Bφ are different, the start of bus cycle may not synchronize with

φ or Bφ according to the bus cycle initiation timing. In this case, clock synchronization cycle

(Tsy) is inserted at the beginning of each bus cycle.

For example, if an external address space access occurs when the frequency rate of I

φ and Bφ is

n : 1, 0 to n-1 cycles of Tsy may be inserted. If an internal peripheral module access occurs when

the frequency rate of I

φ and Pφ is m : 1, 0 to m-1 cycles of Tsy may be inserted.

Figure 6.6 shows the external 2-state access timing when the frequency rate of I

φ and Bφ is 4 : 1.

Figure 6.7 shows the external 3-state access timing when the frequency rate of I

φ and Bφ is 2 : 1.

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