H8SX1663 datasheet(227/1158 Pages) RENESAS

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Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 175 of 1102

REJ09B0294-0100

Name

Symbol

I/O

Function

Output enable/clock enable

OE/CKE

Output

•

Output enable signal for DRAM

•

Clock enable signal for SDRAM

SDRAM

Output

SDRAM dedicated clock

Wait

WAIT

Input

Wait request signal when accessing external address

space

Bus request

BREQ

Input

Request signal for release of bus to external bus

master

Bus request acknowledge

BACK

Output

Acknowledge signal indicating that bus has been

released to external bus master

Bus request output

BREQO

Output

External bus request signal used when internal bus

master accesses external address space in the

external-bus released state

Data transfer acknowledge 3

(DMAC_3)

DACK3

Output

Data acknowledge signal for DMAC_3 single address

transfer

Data transfer acknowledge 2

(DMAC_2

DACK2

Output

Data acknowledge signal for DMAC_2 single address

transfer

Data transfer acknowledge 1

(DMAC_1)

DACK1

Output

Data acknowledge signal for DMAC_1 single address

transfer

Data transfer acknowledge 0

(DMAC_0)

DACK0

Output

Data acknowledge signal for DMAC_0 single address

transfer

External bus clock

Output

External bus clock

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