H8SX1663 datasheet(242/1158 Pages) RENESAS

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Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 190 of 1102

REJ09B0294-0100

Longword

Access

Address

Access

Count

Data

Size

Byte

Word

1st

2nd

1st

2nd

3rd

4th

Bus

Cycle

Data Size

Data bus

D15

D8 D7

LHWR/LUB

LLWR/LLB

Strobe signal

Figure 6.12 Access Sizes and Data Alignment Control for 8-Bit Access Space

(Little Endian)

(2) 16-Bit Access Space

With the 16-bit access space, the upper byte data bus (D15 to D8) and lower byte data bus (D7 to

D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one

word.

Figures 6.13 and 6.14 illustrate data alignment control for the 16-bit access space. Figure 6.13

shows the data alignment when the data endian format is specified as big endian. Figure 6.14

shows the data alignment when the data endian format is specified as little endian.

In big endian, byte access for an even address is performed by using the upper byte data bus and

byte access for an odd address is performed by using the lower byte data bus.

In little endian, byte access for an even address is performed by using the lower byte data bus, and

byte access for an odd address is performed by using the third byte data bus.

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