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H8SX1663 数据表(PDF) 239 Page - Renesas Technology Corp |
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H8SX1663 数据表(HTML) 239 Page - Renesas Technology Corp |
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239 / 1158 page  Section 6 Bus Controller (BSC) Rev.1.00 Jun. 07, 2006 Page 187 of 1102 REJ09B0294-0100 (6) Area 5 Area 5 includes the on-chip RAM and access prohibited spaces. In external extended mode, area 5, other than the on-chip RAM and access prohibited spaces, is external address space. Note that the on-chip RAM is enabled when the RAME bit in SYSCR are set to 1. If the RAME bit in SYSCR is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are an external address space. For details, see section 3, MCU Operating Modes. When area 5 external address space is accessed, the CS5 signal can be output. Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O interface can be selected for area 5 by the MPXE5 bit in MPXCR and the BCSEL5 bit in SRAMCR. Table 6.12 shows the external interface of area 5. Table 6.12 Area 5 External Interface Register Setting Interface MPXE5 of MPXCR BCSEL5 of SRAMCR Basic bus interface 0 0 Byte control SRAM interface 0 1 Address/data multiplexed I/O interface 1 0 Setting prohibited 1 1 |
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