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H8SX1663 数据表(PDF) 235 Page - Renesas Technology Corp |
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H8SX1663 数据表(HTML) 235 Page - Renesas Technology Corp |
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235 / 1158 page  Section 6 Bus Controller (BSC) Rev.1.00 Jun. 07, 2006 Page 183 of 1102 REJ09B0294-0100 Number of access cycles in the SDRAM interface = number of precharge cycles (1 to 4) + number of row address output cycles (1 to 4) + number of column address output cycles (read: 2 to 4, write: 2) + number of clock suspend cycles (only read: 0 or 1) + number of write precharge delay cycles (only write: 0 or 1) Table 6.6 lists the number of access cycles for each interface. Table 6.6 Number of Access Cycles [Legend] Number enclosed by bracket: Number of access cycles n: Pin wait (0 to ∞) m: Number of burst accesses (0 to 63) s: Time for a transition to or from software standby mode Basic bus interface Byte-control SRAM interface Burst ROM interface Address/data multiplexed I/O interface DRAM inter- face SDRAM interface Full access Fast page Refresh Self-refresh Setting mode register Full access (read) Full access (write) Page access (read) Page access (write) Cluster transfer (read) Cluster transfer (write) Refresh Self-refresh = = = = = = =Tma [2,3] =Tma [2,3] =Tp [1 to 4] = =TRp [1 to 4] =TRp [1 to 4] = = = = = = = = = = = Th [0,1] Th [0,1] Th [0,1] Th [0,1] Th [0,1] Th [0,1] +Th [0,1] +Th [0,1] +Tr [1] +TRrw [0 to 3] +TRrw [0 to 3] Tp [1 to 4] Tp [1 to 4] Tp [1 to 4] Tp [1 to 4] Tp [1 to 4] TRp [1 to 4] TRp [1 to 4] +T1 [1] +T1 [1] +T1 [1] +T1 [1] +T1 [1] +T1 [1] +T1 [1] +T1 [1] +Trw [0 to 3] +TRr [1] +TRr [1] +Tr [1] +Tr [1] +Tr [1] +Tr [1] +Tr [1] +TRr [1] +TRr [1] +T2 [1] +T2 [1] +T2 [1] +T2 [1] +T2 [1] +T2 [1] +T2 [1] +T2 [1] +TC1 [1] TC1 [1] +TRc1 [1] + +Trw [0 to 3] +Trw [0 to 3] +Trw [0 to 3] +Trw [0 to 3] +Trw [0 to 3] +TRc1 [1] + +Tt [0,1] +Tt [0,1] +Tt [0,1] +Tt [0,1] +Tt [0,1] +Tt [0,1] +Tc3 [0,1] +Tc3 [0,1] +TRc4 [1] +Tsp [0,1] +Tsp [0,1] +TRp [0 to 7] [2 to 4] [3 to 12+n] [2 to 4] [3 to 12+n] [(2 to 3)+(1 to 8) x m] [(2 to 11+n)+(1 to 8) x m] [4 to 7] [5 to 15+n] [4 to 18+n] [2 to 10+n] [4 to 17] [5 to 18+s] [4 to 11] [5 to 14] [4 to 11] [3 to 6] [2 to 3] [5 to 44] [3 to 36] [4 to 41] [2 to 33] [4 to 14] [5 to 15+s] +Tb [(1 to 8) x m] +Tb [(1 to 8) x m] +TRp [0 to 7] +Tc2 [1] +Tc2 [1] +Tc2 [1] [1] +Tc2 [1] +Tc2 [1] +Tc2 [1] +Tc2 [1] +Tc2 [1] +Tc2 [1] +Trwl [0,1] +Trwl [0,1] +Tcb [0 to 31] +Tcb [0 to 31] +Trwl [0,1] +Tpw [0 to 7] +Tpw [0 to 7] +Tpw [0 to 7] +Tpw [0 to 7] +Tpw [0 to 7] +Tpw [0 to 7] +TRcw [0 to 7] +Tc1 [1] +Tc1 [1] +Tc1 [1] Tc1 [1] Tc1 [1] +Tc1 [1] Tc1 [1] +Tc1 [1] Tc1 [1] +TRcw [0 to 7] +Ttw [n] +Ttw [n] +Ttw [n] +Ttw [n] +Ttw [n] +Ttw [n] +TRc2 [1] +Tcb [0 to 31] +Tcb [0 to 31] +TRc2 [1] +TRc2 [1] +T3 [1] +T3 [1] +T3 [1] +T3 [1] +Tc2 [1] +Tc2 [1] +TRc3 [1] +Tcl [1 to 3] +Tcl [1 to 3] +Tcl [1 to 3] +Tcl [1 to 3] +TRc3 [1] Software standby mode [1+s] Software standby mode [1+s] |
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